V1 validation history

This page preserves V1 development measurements and commands from their original revisions. Current V2 functional instructions are in verification; the stock TT qualification procedure defines V2 physical approval and provenance. The earlier V1 workflow commands below are historical, not the V2 dispatch interface.

V1 development status recorded in September 2026

V1 is implemented and functional verification passes. The latest local candidate from PR #9 passes routed electrical checks at 1.5 ns. Full same-revision physical and gate-level acceptance is mandatory before release. See published releases for accepted source revisions, workflow runs, and retained artifacts. Development merges are not physical acceptance; no FPGA or silicon operation is claimed.

Last failing CI physical source: c22a3d440bb1bf25fe691259c937f95bc4e683c3. Run 35460188674 passed its functional job and failed the enforced slew checks. Its precheck, gate-level, and final acceptance jobs were consequently skipped.

Last failing CI candidate metric	Result
Python tests	176 passed
RTL suites	3 core differential + 3 pin-level passed
Lint / formal induction	Passed
Die / target	1289.28 x 710.64 um (6x4) / 40 ns (25 MHz)
Standard-cell area / utilization, excluding filler	241531 um2 / 26.7649%
Worst routed setup / hold slack	+21.090696 / +0.100768 ns
Slew violations, fast / slow / typical	0 / 125 / 23
Fanout violations	1 at each corner
Capacitance / Magic DRC / LVS errors	0 / 0 / 0

Slew counts use the candidate’s conservative 1.5 ns constraint; they cannot be compared directly with counts under the earlier library limits. Positive setup/hold slack is not electrical signoff or an Fmax measurement. Available placement area is not a guarantee of equivalent capacity for new features.

Earlier local closure checkpoint

The native ARM64 LibreLane 3.1.0.dev3 container completed synthesis through routing, extraction, and final STA locally. Physical inputs match draft commit 3056a35; the captured manifest records the earlier c22a3d4 plus dirty inputs, with hashes identifying the exact configuration. This is development evidence, not clean-checkout release acceptance.

Explicit nominal layer/via RC initialization improved the repair path:

Local extracted result	Value
Standard-cell area / utilization	242867 um2 / 26.9129%
Worst setup / hold slack	+21.217341 / +0.106257 ns
Fanout / capacitance / routing DRC / antenna violations	0 / 0 / 0 / 0
Slew violations, fast / slow / typical at 1.5 ns	0 / 90 / 0
Worst reported slow-corner slew	2.297081 ns

The worst slew is below the library’s 2.5074 ns default, but the current candidate enforces the stricter 1.5 ns target and therefore still fails its configured electrical gate. Do not silently change or suppress that target. The shortened run did not execute final layout DRC/LVS, precheck, gate-level regression, or release acceptance. Its original tool exit code was zero because it stopped before the checker steps; the local runner now separately rejects missing or violating routed metrics, and correctly rejects this run.

Local electrical closure, 2026-09-23

The 55% global-route slew repair margin accommodates the measured difference between estimated and extracted wire capacitance; the final transition limit remains 1.5 ns. See the diagnosis. The local route/extraction/STA checkpoint protocol-v1-route-01 passed:

Local extracted result	Value
Python tests / RTL suites / lint / formal / synthesis	205 / 6 / passed / passed / passed
Standard-cell area / utilization	244113 um2 / 27.0510%
Worst setup / hold slack	+21.053364 / +0.106182 ns
Slew / fanout / capacitance violations, all corners	0 / 0 / 0
Routing DRC / antenna violations	0 / 0
Unannotated signal nets, all corners	0

The manifest records base 88f5210 plus dirty input hashes. Physical config SHA-256: 38bf9b73fb2e324455dc9cd94eeaa75fe819dedf406c5b42ca561155153b9e92. This establishes local routed closure, not release acceptance. Final layout DRC/LVS, precheck, and matching gate-level tests require the full workflow on the final release revision. The release checker rejects changed or missing transition constraints even when electrical violation counts are zero.

Evidence history

• Scaffold fe0a027: GDS, precheck, and gate-level passed. This tiny combinational baseline validates flow setup, not the engine.

• Integrated b8493a4: physical run completed GDS and nine prechecks but gate-level elaboration lacked the IHP UDP primitives. It had 55 slow-corner slew and 123 fanout violations; standard-cell area was 235839 um2. The older checker did not enforce these electrical metrics. This was not a release-quality physical pass.

• The model-source fix includes sg13cmos5l_udp.v. All three pin suites passed locally on that routed netlist and again on the f3e605e routed netlist, including UART at both rates. Those results do not transfer signoff to a later netlist and do not resolve electrical violations.

• f3e605e: first closure run reduced fanout violations to three but retained 55 slow-corner slew violations. c22a3d4 added a post-antenna repair pass and tightened slew; its results are above. Neither candidate is accepted.

Failed and cancelled runs remain visible as history; neither supplies passing acceptance evidence. Experiment details belong with the draft closure PR, not in the product requirements or the Phase 2 feature list.

Verification scope and retained artifacts

Core differential tests compare more than 26,000 system cycles, including twelve deterministic random seeds. Pin-level tests independently decode both UART rates and test concurrent SPI traffic, starvation, and interruption safety. See verification for proof assumptions and coverage limits.

The release workflow retains Python JUnit, both RTL XML reports, formal logs, waveforms, random programs/stimuli, assembled UART firmware, and source/tool/ checksum manifests. Gate-level evidence additionally identifies the routed netlist and primitive models. The physical checker rejects missing or violating slew, fanout, capacitance, geometry, timing, test, and provenance evidence. It requires all nine prechecks and the three named gate-level suites.

Gate-level simulation here is functional routed-netlist simulation; it does not replace extracted STA with a claim of delay-annotated simulation.

Local work and final release gate

Use the local build instructions for iterative optimization. Routine pushes run functional and documentation CI. Expensive GDS workflows are manual, to avoid rebuilding the chip for documentation or intermediate experiment pushes. The full acceptance requirement has not changed.

After local closure, dispatch the full workflow on the exact candidate:

gh workflow run gds.yaml --repo mcranny/protocol-emulator-asic --ref BRANCH
gh run list --repo mcranny/protocol-emulator-asic --workflow gds.yaml

Confirm that the resulting run’s head SHA is the intended source. Require functional, GDS, precheck, gate-level, and acceptance jobs to pass together. After any merge, validate the final release revision rather than assuming the branch’s earlier evidence automatically proves the merged commit.

Direct actions and CMOS5L support tools are pinned. LibreLane is 3.1.0.dev3; IHP-Open-PDK is 2bbec755dc67ca3db0261c3d6163e15735d66710. Nested actions and some dependencies remain dynamically resolved; CI is not fully hermetic.

Download artifacts from the same run to the paths below, then independently check them with the exact workflow head SHA:

python tools/check_physical.py \
  --metrics GDS_logs/runs/wokwi/final/metrics.json \
  --config GDS_logs/runs/wokwi/resolved.json \
  --precheck precheck_reports/results.xml \
  --gatelevel gatelevel_test_results/results.xml \
  --source-commit FULL_WORKFLOW_HEAD_SHA \
  --submission submission/tt_submission/commit_id.json \
  --rtl-manifest functional/build/rtl-evidence.json \
  --gatelevel-manifest gatelevel-evidence/gatelevel-evidence.json \
  --python-tests functional/build/python-results.xml \
  --core-tests functional/test/results_core.xml \
  --formal-log functional/build/formal-engine.log

Here functional is the test-results artifact, and submission is the tt_submission artifact. Retain matching PDK/config/source identities, GDS, netlist, SPEF, metrics, reports, firmware, and test results with the release. Do not tag V1 until every mandatory gate passes. GitHub Pages remains optional.