Protocol Emulator ASIC V2

V2 implements two programmable timing engines, SPI host control, and triggered capture for reproducible hardware debugging. Protocols are ordinary instruction programs. The release candidate selects the validated local TT checkpoint recovery as its physical basis; see the release evidence for source identities, checks and limitations. No hardware demonstration is claimed.

Design and use

• Submission deliverables
• V2 architecture and host interface
  • Architecture
  • Instruction extensions
  • Input filtering
  • Host transport
  • Verification status and limits
  • Reproducing physical feasibility
• V2 ISA reference
  • Base instructions
  • Extensions
  • Timing and ordering
  • Errors, memory and compatibility
• Assembler and toolchain
  • Install and run
  • Assembly, disassembly and image format
  • Model execution
  • Loading and host control
• Executable example programs
  • Protocol matrix
  • Configuration and limits
• V2 host API
• Reset, selection, and state loss
  • Required restart sequence
  • Initializer audit
  • Executable four-state checks
  • Evidence status
• V2 capture
  • Sampling and triggers
  • Records and completion
  • Host access
  • Validation
• Bounded firmware playback
• Protocol fault scenarios and replay
  • Scenario specification
  • Evidence
  • SPI and I2C fault examples
• V1 compatibility
• Project datasheet
  • How it works
  • How to test
  • External hardware

Verification and release

• Verification write-up
  • Independent checks
  • Formal scope
  • Clock/reset crossing review
  • Physical release gate
  • V2 proof and reset scope
  • V2 differential, pin and fault coverage
  • Migration, findings and limitations
• Induction proofs
  • Reset and unconstrained state
  • Memory and execution abstractions
  • Integration assumptions and limitations
• V2 Tiny Tapeout qualification
  • Current status and fixed configuration
  • Repair provenance
  • Candidate approval and hosted execution
  • Six-hour timeout fallback
  • Validated checkpoint recovery
  • Record local evidence in CI
  • Reset-audit addition
• Physical implementation and release evidence
  • Fixed configuration
  • Evidence boundaries
  • Layout and software correspondence
  • Release assembly and publication checklist
• V2.0.0rc1 release candidate notes
  • Candidate behavior
  • Compatibility and operating limits
  • Verification and evidence
  • Qualification and publication checklist
• Track 2: verification after the V2 candidate baseline
• V2 validation
  • Functional checks
  • Physical and acceptance checks
  • Successful baseline and continuing work

Reference and historical evidence

• V1 executable specification
• V2 design evolution
• V1 validation history
• Electrical closure experiments
• Local physical builds
• GDS layout viewers